The present invention relates generally to the control and storage of digital data in a high speed microcomputer system, and in particular, to a method and apparatus for a write back cache controller accommodating a cache memory internal to a system CPU through controlling the system bus and CPU.
The processing speed of microprocessors has increased substantially over the last decade. Years ago this increased processing speed made the addition of smaller, faster and more expensive cache memories to computer system necessary. There are numerous design possibilities for cache memories: direct-mapped or set-associative; write-back or write-through; etc. Much of the savings in high speed systems comes through the use of a write-back (sometimes referred to as copy-back) cache. This type of cache includes memory for data and for status information and a cache controller to handle memory access requests, such that no data is unintentionally lost.
Although the addition of cache memory to main memory met many speed requirements, it became apparent that even the external cache was not enough. The system bus which links the microprocessor to the cache memory contributed to the less than desirable response time. Designers thus began to place a cache memory "internal" to the microprocessor, thus avoiding the bus. For instance, the INTEL CORPORATION of Santa Clara, Calif. produces the 486 family of microprocessors (486SX, 486DX and 486DX2) which all include a write-through cache memory on the NP chip, thereby substantially reducing the system bus load. However, because each of these microprocessors utilize a write-through protocol, every write to the internal cache prompts a memory write on the system bus and incurs associated overhead. If a write-back protocol were to be utilized in a microprocessor internal cache, this would further decrease the number of system bus cycles. However, in a system containing an external cache memory and devices capable of direct memory access or external bus master cache coherency concerns arise.
The INTEL 486 family of microprocessors is utilized in the most popular and widely distributed computer systems. As a result of the popularity of the INTEL 486 family, the 486 bus definition, i.e. the defined signals and their timing, have become an industry standard with more and more chip set and peripheral manufacturers designing their products to work within this definition. Some more pertinent signals available in the 486 bus definition include:
BREQ--The internal cycle pending signal indicates that the microprocessor has internally generated a bus request. BREQ is generated whether or not the microprocessor is driving the bus. PA0 RDY/--The non-burst ready input indicates that the current bus cycle is complete. RDY/ indicates that the external system has presented valid data on the data pins in response to a read or that the external system has accepted data from the microprocessor in response to a write. RDY/ is ignored when the bus is idle and at the end of the first clock of the bus cycle. PA0 BRDY/--The burst ready input performs the same function during a burst cycle that RDY/ performs during a non-burst cycle. BRDY/ is ignored when the bus is idle and at the end of the first clock in a bus cycle. BRDY/ is sampled in the second and subsequent clocks of a burst cycle. PA0 BLAST/--The burst last signal indicates that the next time BRDY/ is returned the burst bus cycle is complete. PA0 LOCK/--The bus lock pin indicates that the current bus cycle is locked. LOCK/ goes active in the first clock of the first locked bus cycle and goes inactive after the last clock of the last locked bus cycle. The last locked cycle ends when ready is returned. PA0 PLOCK/--The pseudo-lock pin indicates that the current bus transaction requires more than one bus cycle to complete. Examples of such operations are floating point long reads and writes (64 bits), segment table descriptor reads (64 bits), in addition to cache line fills (128 bits). The microprocessor will drive PLOCK/ active until the addresses for the last bus cycle of the transaction have been driven regardless of whether RDY/ or BRDY/ have been returned. PA0 ADS/--The address status output indicates that a valid bus cycle definition and address are available on the cycle definition lines and address bus. ADS/ is driven active in the same clock as the addresses are driven. PA0 EADS/--This signal indicates that a valid external address has been driven onto the microprocessor address pins. This address will be used to perform an internal cache invalidation cycle. PA0 M/IO, D/C, W/R--The bus definition signals are not driven during bus hold and follow the timing of the address bus.
INTEL has proposed an approach to utilizing an internal writeback cache, which is being implemented in the INTEL OVERDRIVE processor--a companion chip to the 486DX2. Rather than the standard dirty and validity bit protocol utilized in write-back cache memories, a MESI protocol is used. MESI has four states: Modified, Exclusive, Shared and Invalid. A modified cache line is only available in the internal cache and is different from the main memory (or dirty under the old protocol). An exclusive cache line is available only in the internal cache and is the same as main memory. A shared cache line may exist in an external, as well as the internal cache. An invalid cache line is not available in the internal cache.
It is thus an object of the present invention to provide a cache controller which can insure the coherency of both internal and external caches and main memory.
It is an associated object to provide a cache controller which mimics the microprocessor, such that cache functions are transparent to the system, thus avoiding the need for special controllers to handle special cycles.
These and other objects of the invention will become apparent in light of the present specification and drawings.